Invention Grant
- Patent Title: Method for manufacturing laterally insulated-gate bipolar transistor
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Application No.: US15541155Application Date: 2015-09-28
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Publication No.: US09865702B2Publication Date: 2018-01-09
- Inventor: Feng Huang , Guangtao Han , Guipeng Sun , Feng Lin , Longjie Zhao , Huatang Lin , Bing Zhao , Lixiang Liu , Liangliang Ping , Fengying Chen
- Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
- Applicant Address: CN Wuxi New District, Jiangsu
- Assignee: CSMC Technologies Fab2 Co., Ltd.
- Current Assignee: CSMC Technologies Fab2 Co., Ltd.
- Current Assignee Address: CN Wuxi New District, Jiangsu
- Agency: Hamre, Schumann, Mueller & Larson, P.C.
- Priority: CN201410849111 20141230
- International Application: PCT/CN2015/090965 WO 20150928
- International Announcement: WO2016/107234 WO 20160707
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/739 ; H01L21/02 ; H01L21/311 ; H01L21/265 ; H01L29/06 ; H01L29/40

Abstract:
The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).
Public/Granted literature
- US20170358657A1 METHOD FOR MANUFACTURING LATERALLY INSULATED-GATE BIPOLAR TRANSISTOR Public/Granted day:2017-12-14
Information query
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