Invention Grant
- Patent Title: Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
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Application No.: US15204428Application Date: 2016-07-07
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Publication No.: US09865507B2Publication Date: 2018-01-09
- Inventor: Pinghai Hao , Sameer Pendharkar , Amitava Chatterjee
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/265 ; H01L29/423 ; H01L27/092 ; H01L27/10 ; H01L29/10

Abstract:
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
Public/Granted literature
- US20160322263A1 LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE Public/Granted day:2016-11-03
Information query
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