Invention Grant
- Patent Title: Cascode voltage generating circuit and method
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Application No.: US14826017Application Date: 2015-08-13
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Publication No.: US09755632B2Publication Date: 2017-09-05
- Inventor: Vikas Rana , Fabio De Santis
- Applicant: STMicroelectronics International N.V. , STMicroelectronics S.r.l.
- Applicant Address: NL Amsterdam IT Agrate Brianza
- Assignee: STMICROELECTRONICS INTERNATIONAL N.V.,STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS INTERNATIONAL N.V.,STMICROELECTRONICS S.R.L.
- Current Assignee Address: NL Amsterdam IT Agrate Brianza
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: H03L5/00
- IPC: H03L5/00 ; H03K17/10

Abstract:
A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
Public/Granted literature
- US20170047909A1 CASCODE VOLTAGE GENERATING CIRCUIT AND METHOD Public/Granted day:2017-02-16
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