Invention Grant
- Patent Title: Semiconductor integrated circuit, latch circuit, and flip-flop circuit
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Application No.: US15188616Application Date: 2016-06-21
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Publication No.: US09755622B2Publication Date: 2017-09-05
- Inventor: Kazuyuki Nakanishi
- Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2013-273257 20131227
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/037 ; H03K3/012
Abstract:
A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.
Public/Granted literature
- US20160301397A1 SEMICONDUCTOR INTEGRATED CIRCUIT, LATCH CIRCUIT, AND FLIP-FLOP CIRCUIT Public/Granted day:2016-10-13
Information query
IPC分类:
