- Patent Title: Self-aligned contact metallization for reduced contact resistance
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Application No.: US14981206Application Date: 2015-12-28
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Publication No.: US09754940B2Publication Date: 2017-09-05
- Inventor: Glenn A. Glass , Anand S. Murthy , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H01L29/16
- IPC: H01L29/16 ; H01L27/092 ; H01L21/8238 ; H01L29/417 ; H01L29/66 ; H01L29/165 ; H01L21/8258 ; H01L27/06 ; H01L21/285 ; H01L29/20 ; H01L23/535 ; H01L29/06 ; H01L29/08 ; H01L29/267 ; H01L21/28 ; H01L29/51 ; H01L29/78 ; H01L21/768
Abstract:
Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,
Public/Granted literature
- US20160118384A1 SELF-ALIGNED CONTACT METALLIZATION FOR REDUCED CONTACT RESISTANCE Public/Granted day:2016-04-28
Information query
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