- Patent Title: Method of forming wafer-level molded structure for package assembly
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Application No.: US14798061Application Date: 2015-07-13
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Publication No.: US09754917B2Publication Date: 2017-09-05
- Inventor: Tsung-Ding Wang , Bo-I Lee , Chien-Hsun Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L21/78 ; H01L21/67 ; H01L21/683 ; H01L23/31 ; H01L25/065 ; H01L25/00 ; B32B37/02 ; B32B38/00
Abstract:
A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.
Public/Granted literature
- US20150318271A1 Method of Forming Wafer-Level Molded Structure for Package Assembly Public/Granted day:2015-11-05
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