Invention Grant
- Patent Title: Dummy structure for chip-on-wafer-on-substrate
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Application No.: US15243527Application Date: 2016-08-22
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Publication No.: US09754831B2Publication Date: 2017-09-05
- Inventor: Pei-Ching Kuo , Yi-Hsiu Chen , Jun-Lin Yeh , Yung-Chi Lin , Li-Han Hsu , Wei-Cheng Wu , Ku-Feng Yang , Wen-Chih Chiou
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48 ; H01L23/00 ; H01L23/528 ; H01L23/522 ; H01L23/532

Abstract:
Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
Public/Granted literature
- US20160358818A1 Dummy Structure for Chip-on-Wafer-on-Substrate Public/Granted day:2016-12-08
Information query
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