Invention Grant
- Patent Title: Nonvolatile semiconductor memory device which performs improved erase operation
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Application No.: US15245892Application Date: 2016-08-24
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Publication No.: US09754672B2Publication Date: 2017-09-05
- Inventor: Jun Nakai , Noboru Shibata
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minto-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minto-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-182485 20100817
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/16 ; G11C16/14 ; G11C16/34 ; G11C16/26

Abstract:
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
Public/Granted literature
- US20160365153A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION Public/Granted day:2016-12-15
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