In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.