A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal.