Invention Grant
- Patent Title: Method for a stage optimized high speed adder
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Application No.: US14214049Application Date: 2014-03-14
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Publication No.: US09753691B2Publication Date: 2017-09-05
- Inventor: Mohammad Abdallah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- Main IPC: G06F7/50
- IPC: G06F7/50 ; G06F7/504 ; G06F9/30 ; H04L12/66
Abstract:
A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage.
Public/Granted literature
- US20140324937A1 METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER Public/Granted day:2014-10-30
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