Image sensor pixels having low full-well capacity and high sensitivity for applications such as DIS, qDIS, single/multi bit QIS. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate. Image sensor may also comprise an array of pixels, wherein each pixel comprises: a vertical bipolar structure including an emitter, base, collector configured for storing photocarriers in the base; and a reset transistor coupled to the base, configured to be completely reset of all free carriers using the reset transistor. The emitter may be configured as a pinning layer to facilitate full depletion of the base. Such image sensor pixels may have a full well capacity less than that giving good signal-to-noise ratio (SNR).