Invention Grant
- Patent Title: Via pre-fill on back-end-of-the-line interconnect layer
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Application No.: US14926469Application Date: 2015-10-29
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Publication No.: US09728503B2Publication Date: 2017-08-08
- Inventor: Chao-Hsien Peng , Chi-Liang Kuo , Ming-Han Lee , Hsiang-Huan Lee , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L23/532 ; H01L23/522 ; H01L21/768 ; H01L23/528

Abstract:
In some embodiments, the present disclosure relates to a conductive interconnect layer. The conductive interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening.
Public/Granted literature
- US20160049373A1 VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER Public/Granted day:2016-02-18
Information query
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