Invention Grant
- Patent Title: Alignment of three dimensional integrated circuit components
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Application No.: US14568356Application Date: 2014-12-12
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Publication No.: US09721855B2Publication Date: 2017-08-01
- Inventor: Joseph Kuczynski , Phillip V. Mann , Kevin M. O'Connell , Arvind K. Sinha , Karl Stathakis
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Wood, Herron & Evans, LLP
- Agent Robert R. Williams
- Main IPC: B23K3/047
- IPC: B23K3/047 ; B23K3/08 ; H01L23/00 ; H01L21/66 ; B23K1/00 ; B23K1/20 ; B23K3/06

Abstract:
A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.
Public/Granted literature
- US20160172324A1 ALIGNMENT OF THREE DIMENSIONAL INTEGRATED CIRCUIT COMPONENTS Public/Granted day:2016-06-16
Information query
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