Invention Grant
- Patent Title: Cutting fins and gates in CMOS devices
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Application No.: US15337189Application Date: 2016-10-28
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Publication No.: US09721848B1Publication Date: 2017-08-01
- Inventor: Huiming Bu , Kangguo Cheng , Andrew M. Greene , Dechao Guo , Sivananda K. Kanakasabapathy , Gauri Karve , Balasubramanian S. Pranatharthiharan , Stuart A. Sieg , John R. Sporre , Gen Tsutsui , Rajasekhar Venigalla , Huimei Zhou
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/66 ; H01L27/092 ; H01L29/08 ; H01L29/06 ; H01L29/78
Abstract:
A semiconductor device includes a first fin and a second fin arranged on a substrate, a gate stack arranged over a channel region of the first fin, and spacers arranged along sidewalls of the gate stack. A cavity is arranged adjacent to a distal end of the gate stack. The cavity is defined by the substrate, a distal end of the second fin, and the spacers. A dielectric fill material is arranged in the cavity such that the dielectric fill material contacts the substrate, the distal end of the second fin, and the spacers.
Information query
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