A phase to digital converter determines whether a phase of an internal clock advances or delays with respect to an input serial signal and outputs a first determination code, a determination circuit outputs, for each of first periods, a second determination code based on a plurality of the first determination codes, a gain control code generator circuit generates a gain control code based on a total sum of the first determination codes during the first period, and a phase adjustment code generator circuit gives a gain in accordance with the gain control code to the second determination code, and generates and outputs a phase adjustment code so that the phase of the internal clock is adjusted to make the phase of the internal clock follow the input serial signal.