Invention Grant
- Patent Title: Dynamic clock synchronization
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Application No.: US15198303Application Date: 2016-06-30
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Publication No.: US09698796B2Publication Date: 2017-07-04
- Inventor: Hideyuki Sekiguchi
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2015-142994 20150717
- Main IPC: G06F1/12
- IPC: G06F1/12 ; H03L7/00 ; H03L3/00

Abstract:
A semiconductor device includes: a clock synchronizing circuit that operates in synchronization with a clock; an enable signal generating circuit that generates an enable signal in an operation period during which the clock synchronizing circuit is operated; and a clock supplying circuit that supplies a clock to the clock synchronizing circuit or stop the supply of the clock according to the enable signal when a clock frequency is equal to or lower than a predetermined frequency, and supply a clock to the clock synchronizing circuit, irrespective of the enable signal, when the clock frequency is higher than the predetermined frequency.
Public/Granted literature
- US20170019113A1 SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE Public/Granted day:2017-01-19
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