Invention Grant
- Patent Title: Strained channel region transistors employing source and drain stressors and systems including the same
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Application No.: US15045666Application Date: 2016-02-17
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Publication No.: US09698265B2Publication Date: 2017-07-04
- Inventor: Van H. Le , Harold W. Kennel , Willy Rachmady , Ravi Pillarisetty , Jack Kavalieros , Niloy Mukherjee
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L29/20 ; H01L29/775 ; B82Y99/00

Abstract:
Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.
Public/Granted literature
- US20160233336A1 STRAINED CHANNEL REGION TRANSISTORS EMPLOYING SOURCE AND DRAIN STRESSORS AND SYSTEMS INCLUDING THE SAME Public/Granted day:2016-08-11
Information query
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