Invention Grant
- Patent Title: 3D chip-on-wafer-on-substrate structure with via last process
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Application No.: US15264245Application Date: 2016-09-13
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Publication No.: US09698081B2Publication Date: 2017-07-04
- Inventor: Chen-Hua Yu , Ming-Fa Chen , Wen-Ching Tsai
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/48 ; H01L23/498 ; H01L23/00 ; H01L21/768 ; H01L21/48 ; H01L21/311 ; H01L23/31 ; H01L21/56 ; H01L23/522 ; H01L25/065 ; H01L25/00

Abstract:
Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
Public/Granted literature
- US20170005027A1 3D Chip-On-Wafer-On-Substrate Structure With Via Last Process Public/Granted day:2017-01-05
Information query
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