Invention Grant
- Patent Title: Integrated circuit
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Application No.: US15265036Application Date: 2016-09-14
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Publication No.: US09697895B1Publication Date: 2017-07-04
- Inventor: Koichiro Zaitsu
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2016-054528 20160317
- Main IPC: G11C11/16
- IPC: G11C11/16 ; G11C13/00

Abstract:
An integrated circuit according to an embodiment includes: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the plurality of first wiring lines; a plurality of resistive change memory elements provided in cross regions of the plurality of first and second wiring lines, each of which includes a first electrode connected to a corresponding first wiring line, a second electrode connected to a corresponding second wiring line, and a resistive change layer provided between the first and second electrodes, and in each of which a resistive state between the first electrode and the second electrode can be programmed from one of a first resistive state and a second resistive state, which has a larger resistance value than the first resistive state, to the other; and a driver driving the plurality of first and second wiring lines.
Information query