Invention Grant
- Patent Title: Efficient hardware instructions for processing bit vectors for single instruction multiple data processors
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Application No.: US14023249Application Date: 2013-09-10
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Publication No.: US09697174B2Publication Date: 2017-07-04
- Inventor: Amit Ganesh , Shasank K. Chavan , Vineet Marwah , Jesse Kamp , Anindya C. Patthak , Michael J. Gleeson , Allison L. Holloway , Roger Macnicol
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood Shores
- Assignee: ORACLE INTERNATIONAL CORPORATION
- Current Assignee: ORACLE INTERNATIONAL CORPORATION
- Current Assignee Address: US CA Redwood Shores
- Agency: Hickman Palermo Becker Bingham LLP
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F15/80 ; G06F17/30

Abstract:
A method and apparatus for efficiently processing data in various formats in a single instruction multiple data (“SIMD”) architecture is presented. Specifically, a method to unpack a fixed-width bit values in a bit stream to a fixed width byte stream in a SIMD architecture is presented. A method to unpack variable-length byte packed values in a byte stream in a SIMD architecture is presented. A method to decompress a run length encoded compressed bit-vector in a SIMD architecture is presented. A method to return the offset of each bit set to one in a bit-vector in a SIMD architecture is presented. A method to fetch bits from a bit-vector at specified offsets relative to a base in a SIMD architecture is presented. A method to compare values stored in two SIMD registers is presented.
Public/Granted literature
- US20140013077A1 EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS Public/Granted day:2014-01-09
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