Invention Grant
- Patent Title: Testing apparatus and method for microcircuit and wafer level IC testing
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Application No.: US14328460Application Date: 2014-07-10
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Publication No.: US09696347B2Publication Date: 2017-07-04
- Inventor: John DeBauche , Dan Campion , Michael Andres , Steve Rott , Jeffrey Sherry , Brian Halvorson , Brian Eshult
- Applicant: Johnstech International Corporation
- Applicant Address: US MN Minneapolis
- Assignee: Johnstech International Corporation
- Current Assignee: Johnstech International Corporation
- Current Assignee Address: US MN Minneapolis
- Agency: Altera Law Group, LLC
- Main IPC: G01R3/00
- IPC: G01R3/00 ; G01R1/067 ; G01R1/073

Abstract:
The test system provides an array of test probes having a cross beam. The probes pass through a first or upper probe guide retainer which has a plurality of slot sized to receive the probes in a way that they cannot rotate. The probes are biased upwardly through the retainer by an elastomeric block having a similar array of slots. The elastomer is then capped at its bottom by a second or lower retainer with like slots to form a sandwich with the elastomer therebetween. The bottom ends of the probes are group by probe height. A plurality of flex circuits at the different heights engage bottom probe ends at their respective height levels and take continue the circuits to a probe card where test signals originate.
Public/Granted literature
- US20150015287A1 TESTING APPARATUS AND METHOD FOR MICROCIRCUIT AND WAFER LEVEL IC TESTING Public/Granted day:2015-01-15
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