A phase error detector includes an N counter configured to frequency-divide a first clock by N, and output a signal at predetermined timing, an M counter configured to frequency-divide a second clock by M, and output a signal at predetermined timing, a comparator configured to perform phase comparison between a phase when a value of the N counter is 0 and a phase when a value of the M counter is 0, and perform phase comparison between a phase when a value of the N counter is equal to a value obtained by dividing N into a substantially predetermined value and a phase when a value of the M counter is equal to a value obtained by dividing M into a substantially predetermined value and a synthetic circuit configured to generate a phase error, based on comparison results of the comparator.