Invention Grant
- Patent Title: Semiconductor device and manufacturing method thereof
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Application No.: US15052114Application Date: 2016-02-24
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Publication No.: US09680031B2Publication Date: 2017-06-13
- Inventor: Hiroshi Sunamura , Kishou Kaneko , Yoshihiro Hayashi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2012-195291 20120905
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L27/088 ; H01L29/66 ; H01L21/822 ; H01L23/522 ; H01L23/532 ; H01L27/06 ; H01L27/12 ; H01L29/792

Abstract:
Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.
Public/Granted literature
- US20160172504A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2016-06-16
Information query
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