Invention Grant
- Patent Title: Methods for integrated circuit fabrication with protective coating for planarization
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Application No.: US14685525Application Date: 2015-04-13
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Publication No.: US09679781B2Publication Date: 2017-06-13
- Inventor: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar Murali Subramanian
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01R9/00
- IPC: H01R9/00 ; H05K3/00 ; H01L21/3105 ; H01L21/033 ; H01L21/306 ; H01L21/311

Abstract:
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
Public/Granted literature
- US20150287610A1 METHODS FOR INTEGRATED CIRCUIT FABRICATION WITH PROTECTIVE COATING FOR PLANARIZATION Public/Granted day:2015-10-08
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