Invention Grant
- Patent Title: Leakage current reduction in stacked field-effect transistors
-
Application No.: US14465003Application Date: 2014-08-21
-
Publication No.: US09673805B2Publication Date: 2017-06-06
- Inventor: Sarveswara Bade , Shiu Chung Ho , Marcel A. Kossel , Pradeep Thiagarajan
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Kennedy Lenart Spraggins LLP
- Agent Brandon C. Kennedy; Steven Meyers
- Main IPC: H03K17/16
- IPC: H03K17/16 ; G01R31/00

Abstract:
A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.
Public/Granted literature
- US20160056809A1 LEAKAGE CURRENT REDUCTION IN STACKED FIELD-EFFECT TRANSISTORS Public/Granted day:2016-02-25
Information query