Invention Grant
- Patent Title: Input buffer with selectable hysteresis and speed
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Application No.: US15235074Application Date: 2016-08-11
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Publication No.: US09673788B2Publication Date: 2017-06-06
- Inventor: Yi Zhao , Dongling Zhang
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Agent Charles E. Bergere
- Priority: CN201510723963 20150908
- Main IPC: H03K3/356
- IPC: H03K3/356 ; H03K3/012 ; H03K3/3565

Abstract:
A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage.
Public/Granted literature
- US20170070213A1 INPUT BUFFER WITH SELECTABLE HYSTERESIS AND SPEED Public/Granted day:2017-03-09
Information query
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