Invention Grant
- Patent Title: Method of semiconductor fabrication with height control through active region profile
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Application No.: US14975525Application Date: 2015-12-18
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Publication No.: US09673112B2Publication Date: 2017-06-06
- Inventor: Yi-Cheng Chao , Che-Cheng Chang , Po-Chi Wu , Jung-Jui Li
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chi
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chi
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/762

Abstract:
The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions.
Public/Granted literature
- US20160240444A1 Method of Semiconductor Fabrication with Height Control Through Active Region Profile Public/Granted day:2016-08-18
Information query
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