Invention Grant
- Patent Title: Method of patterning incorporating overlay error protection
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Application No.: US14863991Application Date: 2015-09-24
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Publication No.: US09673050B2Publication Date: 2017-06-06
- Inventor: Anton J. deVilliers , Jeffrey Smith
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/033

Abstract:
Techniques herein include use of a spacer processes for patterning flows during microfabrication for creating hardmasks, features, contact openings, etc. Techniques herein include using a sidewall spacer to define a hard border between features to be patterned. Such a spacer is positioned underneath an overlying relief pattern so that a portion of the spacer is exposed and protecting an underlying layer. Techniques herein can be used for metallization, and, in particular, metallization of a first metal layer above electronic device contacts. More broadly, techniques herein can be used for any type of critical placement where one structure is extremely close to another structure, such as with sub-resolution dimensions.
Public/Granted literature
- US20160133464A1 Method of Patterning Incorporating Overlay Error Protection Public/Granted day:2016-05-12
Information query
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