Invention Grant
- Patent Title: Apparatus and method of programming and verification for a nonvolatile semiconductor memory device
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Application No.: US14014125Application Date: 2013-08-29
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Publication No.: US09672926B2Publication Date: 2017-06-06
- Inventor: Yasuhiro Shiino , Nobushi Matsuura , Masashi Yoshida , Eietsu Takahashi
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2013-104179 20130516
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C16/34 ; G11C11/56 ; G11C16/04

Abstract:
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to repeat a program operation and a verify operation. The control circuit performs a first verify operation of sensing whether threshold voltages of selected memory cells are greater than or equal to a first threshold voltage, and a second verify operation of sensing whether the threshold voltages of the selected memory cells are greater than or equal to a second threshold voltage (first threshold voltage
Public/Granted literature
- US20140340964A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2014-11-20
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