Dual-Port SRAM cells are described. In an embodiment, a cell includes first and second pull-down, first and second pull-up, and first through fourth pass-gate transistors. Each transistor includes a first source/drain region in an active area, a channel extending above the active area, and a second source/drain region above the channel. First source/drain regions of pull-down transistors are electrically coupled through a first active area. First source/drain regions of pull-up transistors are electrically coupled through a second active area. A first, and a second, gate electrode is around channels of the first, and second, pull-down and pull-up transistors, respectively. Second source/drain regions of the first pull-down, first pull-up, and first and third pass-gate transistors are electrically coupled to the second gate electrode. Second source/drain regions of the second pull-down, second pull-up, and second and fourth pass-gate transistors are electrically coupled to the first gate electrode.