Invention Grant
- Patent Title: Technique of reducing shallow trench isolation loss during fin formation in finFETs
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Application No.: US14991184Application Date: 2016-01-08
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Publication No.: US09646888B2Publication Date: 2017-05-09
- Inventor: Lijuan Du , Hai Zhao
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN201510033538 20150122
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L21/8234 ; H01L29/66 ; H01L21/762 ; H01L21/311 ; H01L21/033 ; H01L29/78 ; H01L27/088 ; H01L21/3115

Abstract:
A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer, etching to the semiconductor substrate to form a fin-type structure and a groove; forming an isolation material layer in the regions between adjacent fins of the fin-type structure and in the groove; removing a portion of the isolation material layer that is located above the hard mask layer to form a shallow trench isolation; and forming a second mask layer over the hard mask layer, the second mask layer having an opening above the shallow trench isolation; performing ion implantation to the shallow trench isolation through the opening; removing the second mask layer and the hard mask layer; and removing a portion of the isolation material layer located in the regions between adjacent fins of the fin-type structure and a portion of the shallow trench isolation.
Public/Granted literature
- US20160218041A1 TECHNIQUE OF REDUCING SHALLOW TRENCH ISOLATION LOSS DURING FIN FORMATION IN FINFETS Public/Granted day:2016-07-28
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