Invention Grant
- Patent Title: Semiconductor dielectric interface and gate stack
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Application No.: US14464434Application Date: 2014-08-20
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Publication No.: US09646823B2Publication Date: 2017-05-09
- Inventor: Chien-Hsun Wang , Shih-Wei Wang , Gerben Doornbos , Georgios Vellianitis , Matthias Passlack
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/28 ; H01L29/51 ; H01L21/306 ; H01L29/66 ; H01L29/78

Abstract:
A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.
Public/Granted literature
- US20140353771A1 Semiconductor Dielectric Interface and Gate Stack Public/Granted day:2014-12-04
Information query
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