Approaches for a comparative ESD protection scheme are provided. An electrostatic discharge (ESD) clamping circuit includes: a discharge field effect transistor (FET) connected between a power supply node and ground; and a comparator that receives a divided power supply voltage at a first input and a reference voltage at a second input. The comparator outputs a first value that turns the discharge FET on when the divided power supply voltage is greater than the reference voltage. The comparator outputs a second value that turns the discharge FET off when the divided power supply voltage is less than or equal to the reference voltage.