A planar MOSFET is provided on the upper surface of the N−-type semiconductor substrate in a mesa portion between the trenches. A P+-type emitter layer is provided between the trench and the planar MOSFET in the mesa portion. A P-type collector layer is provided on a lower surface of the N−-type semiconductor substrate. The planar MOSFET includes an N+-type emitter layer, an upper portion of the N−-type semiconductor substrate, a P-type base layer, and a planar gate on the foregoing with a gate insulating film interposed therebetween. The planar gate is connected to the gate trench. The P+-type emitter layer has a higher impurity concentration than the P-type base layer and has an electric potential equal to an emitter potential of the N+-type emitter layer. The N+-type emitter layer is not in contact with the trench. A trench MOSFET is not formed.