Invention Grant
- Patent Title: Write assist scheme for low power SRAM
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Application No.: US14282809Application Date: 2014-05-20
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Publication No.: US09640249B2Publication Date: 2017-05-02
- Inventor: Gang Chen , Jing Guo , Jun Yang
- Applicant: Nvidia Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Nvidia Corporation
- Current Assignee: Nvidia Corporation
- Current Assignee Address: US CA Santa Clara
- Priority: CN201410054989 20140218
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/419 ; G11C5/14

Abstract:
A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.
Public/Granted literature
- US20150235695A1 WRITE ASSIST SCHEME FOR LOW POWER SRAM Public/Granted day:2015-08-20
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