Invention Grant
- Patent Title: Control mechanism for fine-tuned cache to backing-store synchronization
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Application No.: US13664387Application Date: 2012-10-30
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Publication No.: US09639466B2Publication Date: 2017-05-02
- Inventor: James Patrick Robertson , Gregory Alan Muthler , Hemayet Hossain , Timothy John Purcell , Karan Mehra , Peter B. Holmqvist , George R. Lynch
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0804 ; G06F12/084 ; G06F12/0895 ; G06F12/0868 ; G06F12/0866

Abstract:
One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.
Public/Granted literature
- US20140122809A1 CONTROL MECHANISM FOR FINE-TUNED CACHE TO BACKING-STORE SYNCHRONIZATION Public/Granted day:2014-05-01
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