Invention Grant
- Patent Title: Placing integrated circuit devices using perturbation
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Application No.: US14141718Application Date: 2013-12-27
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Publication No.: US09638747B2Publication Date: 2017-05-02
- Inventor: Paul J. Diglio , Nader N. Abazarnia , Christopher R. Schroeder , Rene J. Sanchez , Morten S. Jensen
- Applicant: Paul J. Diglio , Nader N. Abazarnia , Christopher R. Schroeder , Rene J. Sanchez , Morten S. Jensen
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R1/04

Abstract:
Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.
Public/Granted literature
- US20150185281A1 PLACING INTEGRATED CIRCUIT DEVICES USING PERTURBATION Public/Granted day:2015-07-02
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