Invention Grant
- Patent Title: Variable gate width for gate all-around transistors
- Patent Title (中): 栅极全能晶体管的可变栅极宽度
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Application No.: US13997162Application Date: 2011-12-30
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Publication No.: US09590089B2Publication Date: 2017-03-07
- Inventor: Willy Rachmady , Van H. Le , Ravi Pillarisetty , Jack T. Kavalieros , Robert S. Chau , Seung Hoon Sung
- Applicant: Willy Rachmady , Van H. Le , Ravi Pillarisetty , Jack T. Kavalieros , Robert S. Chau , Seung Hoon Sung
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/068239 WO 20111230
- International Announcement: WO2013/101230 WO 20130704
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L29/66 ; H01L29/775 ; H01L29/06 ; H01L29/10 ; H01L29/786 ; B82Y10/00 ; B82Y40/00

Abstract:
Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.
Public/Granted literature
- US20130341704A1 VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS Public/Granted day:2013-12-26
Information query
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