Invention Grant
- Patent Title: Interconnect structures for wafer level package and methods of forming same
- Patent Title (中): 晶圆级封装的互连结构及其形成方法
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Application No.: US15174606Application Date: 2016-06-06
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Publication No.: US09589932B2Publication Date: 2017-03-07
- Inventor: Chen-Hua Yu , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/31
- IPC: H01L21/31 ; H01L25/065 ; H01L23/31 ; H01L21/56 ; H01L21/3105 ; H01L23/528 ; H01L23/00 ; H01L21/48 ; H01L23/538 ; H01L21/683 ; H01L25/00 ; H01L21/768 ; H01L23/48 ; H01L23/498
Abstract:
Representative methods are disclosed for fabricating device packages having a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting the molding compound. The molding compound comprises a non-planar top surface, and a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound. The device package further includes a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.
Public/Granted literature
- US20160284667A1 INTERCONNECT STRUCTURES FOR WAFER LEVEL PACKAGE AND METHODS OF FORMING SAME Public/Granted day:2016-09-29
Information query
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