Invention Grant
US09589811B2 FinFET spacer etch with no fin recess and no gate-spacer pull-down
有权
FinFET间隔蚀刻,没有鳍片凹槽,没有栅极隔离层下拉
- Patent Title: FinFET spacer etch with no fin recess and no gate-spacer pull-down
- Patent Title (中): FinFET间隔蚀刻,没有鳍片凹槽,没有栅极隔离层下拉
-
Application No.: US14749020Application Date: 2015-06-24
-
Publication No.: US09589811B2Publication Date: 2017-03-07
- Inventor: Simon Ruffell
- Applicant: Varian Semiconductor Equipment Associates, Inc.
- Applicant Address: US MA Gloucester
- Assignee: Varian Semiconductor Equipment Associates, Inc.
- Current Assignee: Varian Semiconductor Equipment Associates, Inc.
- Current Assignee Address: US MA Gloucester
- Main IPC: H01L21/3065
- IPC: H01L21/3065 ; H01L29/66 ; H01L21/283 ; H01L29/161 ; H01L29/10

Abstract:
A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.
Public/Granted literature
- US20160379832A1 FINFET SPACER ETCH WITH NO FIN RECESS AND NO GATE-SPACER PULL-DOWN Public/Granted day:2016-12-29
Information query
IPC分类: