A memory array has a NVM element with a plurality of FETs. A first set of FETs of the plurality of FETs is coupled to a bitline true of the memory array. The first set of FETs has a first channel width. A second set of FETs of the plurality of FETs is coupled to a bitline complement of the memory array. The second set of FETs has a second channel width. The first channel width is greater than the second channel width. The channel width disparity provides the NVM element of the unprogrammed memory array with a default state.