Invention Grant
- Patent Title: Semiconductor memory with data line capacitive coupling
- Patent Title (中): 半导体存储器与数据线电容耦合
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Application No.: US15066914Application Date: 2016-03-10
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Publication No.: US09589629B2Publication Date: 2017-03-07
- Inventor: Jhon-Jhy Liaw
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C7/12 ; G11C11/412

Abstract:
A method of accessing a semiconductor memory includes operations as follows. A first voltage is received at a first data line, and a second voltage is received at a second data line, during a write operation of the semiconductor memory, in which the first voltage is lower than the second voltage, and a first coupling line is capacitively coupled with the first data line to lower the first voltage at the first data line in the write operation of the semiconductor memory.
Public/Granted literature
- US20160196871A1 SEMICONDUCTOR MEMORY WITH DATA LINE CAPACITIVE COUPLING Public/Granted day:2016-07-07
Information query
IPC分类: