Invention Grant
- Patent Title: Multi-channel delay locked loop
- Patent Title (中): 多通道延时锁定环路
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Application No.: US14810900Application Date: 2015-07-28
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Publication No.: US09564907B2Publication Date: 2017-02-07
- Inventor: Joo-Hyung Chae , Suhwan Kim , Deog-Kyoon Jeong
- Applicant: SK hynix Inc. , SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- Applicant Address: KR Icheon KR Seoul
- Assignee: SK HYNIX INC.,SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- Current Assignee: SK HYNIX INC.,SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
- Current Assignee Address: KR Icheon KR Seoul
- Priority: KR10-2014-0124056 20140918
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/07 ; H03L7/085 ; H03L7/08 ; H03L7/081 ; H03L7/087

Abstract:
A multi-channel delay locked loop includes a global delay locked loop and a plurality of local delay locked loops. The global delay locked loop is configured to lock an input clock signal and output a global delay control signal corresponding to a delay amount of the input clock signal during a locking operation. Each of the plurality of local delay locked loops is configured to output a channel clock signal by locking the input clock signal, and initialize the delay amount of the input clock signal according to the global delay control signal.
Public/Granted literature
- US20160087638A1 MULTI-CHANNEL DELAY LOCKED LOOP Public/Granted day:2016-03-24
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