Invention Grant
US09564516B2 Method of making integrated MOSFET-schottky diode device with reduced source and body kelvin contact impedance and breakdown voltage
有权
制造集成MOSFET肖特基二极管器件的方法，具有降低的源极和体开口接触阻抗和击穿电压
- Patent Title: Method of making integrated MOSFET-schottky diode device with reduced source and body kelvin contact impedance and breakdown voltage
- Patent Title (中): 制造集成MOSFET肖特基二极管器件的方法，具有降低的源极和体开口接触阻抗和击穿电压
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Application No.: US14602274Application Date: 2015-01-22
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Publication No.: US09564516B2Publication Date: 2017-02-07
- Inventor: Ji Pan
- Applicant: Alpha and Omega Semiconductor Incorporated
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: 5Suns
- Agent Chein-Hwa Tsao; Lance A. Li
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/423 ; H01L29/78 ; H01L29/08 ; H01L29/861 ; H01L29/872 ; H01L29/06 ; H01L29/10 ; H01L29/417 ; H01L29/47 ; H01L21/265 ; H01L21/28
Abstract:
A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.
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