Invention Grant
- Patent Title: Non-volatile memory device and corresponding operating method with stress reduction
- Patent Title (中): 非易失性存储器件及相应的减压操作方法
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Application No.: US14970732Application Date: 2015-12-16
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Publication No.: US09564231B2Publication Date: 2017-02-07
- Inventor: Francesca Grande , Alfredo Signorello , SantiNunzioAntonino Pagano , Maria Giaquinta
- Applicant: STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee Address: IT Agrate Brianza (MB)
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: IT102015000018393 20150527
- Main IPC: G11C8/08
- IPC: G11C8/08 ; G11C16/14 ; G11C16/08

Abstract:
A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.
Public/Granted literature
- US20160351264A1 NON-VOLATILE MEMORY DEVICE AND CORRESPONDING OPERATING METHOD WITH STRESS REDUCTION Public/Granted day:2016-12-01
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