Invention Grant
US09564227B2 Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays
有权
存储器件具有耦合到多个存储单元阵列中的每一层的不同源极线
- Patent Title: Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays
- Patent Title (中): 存储器件具有耦合到多个存储单元阵列中的每一层的不同源极线
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Application No.: US14936719Application Date: 2015-11-10
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Publication No.: US09564227B2Publication Date: 2017-02-07
- Inventor: Akira Goda , Zengtao Liu
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C5/02 ; G11C16/04 ; G11C11/56 ; G11C16/28 ; G11C16/26
Abstract:
A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer.
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