A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.