Invention Grant
- Patent Title: Representing a cache line bit pattern via meta signaling
- Patent Title (中): 通过元信号表示高速缓存行位模式
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Application No.: US14142813Application Date: 2013-12-28
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Publication No.: US09563251B2Publication Date: 2017-02-07
- Inventor: Saher Abu Rahme , Christopher E. Cox , Joydeep Ray
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F1/32
Abstract:
A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.
Public/Granted literature
- US20150186282A1 REPRESENTING A CACHE LINE BIT PATTERN VIA META SIGNALING Public/Granted day:2015-07-02
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