Invention Grant
- Patent Title: Multilayer wiring substrate
- Patent Title (中): 多层布线基板
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Application No.: US14889385Application Date: 2014-05-27
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Publication No.: US09538645B2Publication Date: 2017-01-03
- Inventor: Hisashi Kobuke , Yousuke Futamata , Emi Ninomiya
- Applicant: EPCOS AG
- Applicant Address: DE Munich
- Assignee: EPCOS AG
- Current Assignee: EPCOS AG
- Current Assignee Address: DE Munich
- Agency: Slater Matsil, LLP
- Priority: JP2013-115818 20130531
- International Application: PCT/EP2014/060976 WO 20140527
- International Announcement: WO2014/191421 WO 20141204
- Main IPC: H05K1/09
- IPC: H05K1/09 ; H05K1/03 ; H05K1/00 ; H05K3/46 ; C03C12/00 ; H05K1/02 ; H05K1/11

Abstract:
A multilayer wiring substrate includes a number of insulating layers, each insulating layer including a glass ceramic. A number of internal conductor layers are formed between the insulating layers. Via conductors penetrate through the insulating layers and mutually connect the internal conductor layers in different layer locations. Surface conductor layers are formed on an outer surfaces in a lamination direction of the insulating layers. The insulating layers include outside insulating layers and inside insulating layers. A first aspect ratio representing an oblateness and sphericity of an external filler contained in the outside insulating layers is larger than a second aspect ratio representing an oblateness and sphericity of an internal filler contained in the inside insulating layers. A thermal expansion coefficient of the outside insulating layers is smaller than a thermal expansion coefficient of the inside insulating layers.
Public/Granted literature
- US20160088729A1 Multilayer Wiring Substrate Public/Granted day:2016-03-24
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